An integrated circuit (IC) layout specifies portions of various components of an IC. When the IC is to include a large number of registers, latches, flip-flops, and/or other types of clocked devices (“sinks”) that are to be clocked by one or more clocks, the IC must include one or more clock trees for delivering the clock signal from the clock source to all of the sinks to be clocked by it. A clock tree distributes a clock signal from its root (e.g., a clock source) to a set of sinks (e.g., flip flops) within an IC through a branching network of drivers (e.g., buffers or inverters). A single driver distributes the clock signal to a grouping of other drivers and/or sinks. Connectivity between a driver and its fanout components (e.g., other drivers and/or sinks) is described by a “clock net” and will be physically implemented by routed wires.
Electronic design automation (EDA) software systems commonly perform clock-tree synthesis (CTS). Conventional approaches to CTS include building a clock tree by placing drivers at various regions of the IC design based on satisfaction of a set of clock tree design constraints that include timing constraints such as clock skew among others (e.g., clock slew and clock latency). Clock skew refers to a difference in clock arrival time between two clock sinks.
In some instances, clock skew may be intentionally added into a clock tree. Clock skew that is intentionally added into a clock tree is referred to as “useful skew.” During CTS, a clock path delay for each clock sink is tuned in accordance with design constraints. Prior to tuning clock path delays, a pin insertion delay (PID) may be assigned to a clock path and provided as a constraint to CTS. PID is a virtual delay added to a clock path of the IC design that causes CTS to introduce the useful skew when tuning clock path delays.
Conventionally, a global clock skew target is provided as a clock tree design constraint and a fixed skew window for clock sinks in the clock tree is determined based on the clock skew target during CTS. Clock path delays of clock sinks are tuned during CTS such that the difference in clock arrival time between any two sinks falls within the skew window. For example, given a 100 ps clock skew target, CTS will produce a buffered clock tree in which the difference in clock arrival time between any two clock sinks in the clock tree is between Ops and 100 ps. To achieve this clock balancing, clock arrival time at some clock sinks may be delayed compared to a reference delay while clock arrival time at some clock sinks may be advanced compared to the reference delay. The skew window determined during CTS defines a permissible clock arrival delay and advance limit relative to a target delay, which is based on the reference delay.
In instances in which PID is assigned to a clock path of a clock sink to introduce useful skew, the target delay for the clock window is based on an offset applied to the reference delay (also referred to as a “skew offset”) determined based on the PID. However, if the skew window of clock tree is too large, the PID in the clock path may not be honored because the clock sink may be buffered such that the clock arrival time for the clock sink is within the skew window without accounting for the skew offset applied to the target delay based on the PID. For example, the clock path delay of a clock sink may be tuned such that the clock arrival time for the clock sink is near or at the delay or advance limit of the skew window. As a result, the actual useful skew in the resulting clock tree may be diminished or even negated compared to the intended useful skew.